Gigabit Ethernet over Copper: Hardware Architecture and Operation
By Shriram Patwardhan (Issue 4 2001)
1000BaseT extends the envelope of Gigabit Ethernet by enabling operation over the extensive installed base of legacy Category-5 cabling systems. The 1000BaseT architecture provides cost-effective scalability of the network speed from 100 Mbps to 1 Gbps because the same cabling environment can be used for Ethernet, Fast Ethernet, or Gigabit Ethernet. This article describes the hardware architecture and behavior of Gigabit Ethernet over copper from a signal- processing standpoint.
The Category-5 (Cat-5) unshielded twisted pair (UTP) cabling as defined by American National Standards Institute/Telecommunications Industry Association/Electronics Industry Association (ANSI® /TIA/EIA)-568-A is currently the most common data-grade cabling used throughout the world. The 1000BaseT technology taps the widespread use of this cable. Users can run the same network at a gigabit speed without changing the cabling environment. Autonegotiation allows the three Ethernet technologies—Ethernet (10 Mbps), Fast Ethernet (100 Mbps), and Gigabit Ethernet (1000 Mbps)—to co-exist.
Gigabit Ethernet and the Physical layer
Figure 1 illustrates the architecture of the 10/100/1000 Mbps Physical layer (PHY) in the Open Systems Interconnection (OSI) Model.
Figure 1. Functional block diagram of 10/100/1000 PHY
Within the 1000BaseT architecture, the signals between the Media Access Control (MAC) and the PHY interact across the Gigabit Media Independent Interface (GMII). This interface consists of transmit, receive, and clock signal lines. The PHY essentially consists of two blocks: physical coding sublayer (PCS) and physical medium attachment (PMA).
Gigabit Ethernet employs a four-dimensional pulse amplitude modulation-5 (4D-PAM-5) coding scheme. When run over copper, the fundamental difference in the operation of 10/100 Mbps Ethernet and Gigabit Ethernet is that Gigabit operation uses all four unshielded twisted pairs—transmitting and receiving simultaneously on all four pairs; 10/100 Mbps uses only two pairs—one dedicated for transmitting and one dedicated for receiving.
The data that travels between the PCS and the MAC consists of 8 bits, which means 28 = 256 different valid data words are possible. If the 100BaseTX line-coding scheme (Multi-level 3, or MLT-3) is used, only 34 = 81 (less than 256) valid data words are possible because the data is transmitted on all four twisted pairs simultaneously.
If four levels are used, 44 = 256 valid words are possible. However, this approach provides no control signals or redundant data signals to ensure reliable transmission. For this reason, five voltage levels are chosen, which gives 54 = 625 possible code words. Of these, 256 are data words, an additional 256 code words represent the same data words (providing 100 percent redundancy), and the remaining 113 words are used for control and idle signals. Thus, each 8-bit word is coded as a four- dimensional vector of quinary symbols spaced by a time interval of 8 nanoseconds (ns). These symbols are selected from the set {-2, -1, 0, +1, +2}. Figure 2 illustrates the mapping of these symbols into voltage levels.
Figure 2. Symbol mapping and data flow representation on Cat-5 cable
The PCS block converts data to signals
Figure 3 shows the functional block diagram of the PCS. The PCS transmitter consists of several functional blocks that convert the 8-bit Transmit Data (TXD) running on the GMII to PAM-5 symbols to be passed to the PMA function. These functional blocks are described below.
Figure 3. PCS functional block diagram
Linear Feedback Shift Register (LFSR). Scrambling reduces electromagnetic interference by randomizing the transmitted data. The receiver descrambles the scrambled data to recover it. The side-stream scrambler (SSR) function uses a LFSR that implements one of two equations: gM (x) = 1 + x13 + x33 for master operation mode and gs (x) = 1 + x20 + x33 for slave operation mode.
Figure 4 shows the two SSRs. The scrambling sequence is repeated every 68.72 seconds [(233 -1) x 8ns]. The 33-bit data output, Scrn [32:0], of this block is then fed into the data scrambler and symbol sign scrambler word generator.
Figure 4. Master and slave scramblers used in 1000BaseT operation
Data and symbol sign scrambler word generator. The word generator uses Scrn [32:0] to generate further scrambled values: Sxn [3:0], Syn [3:0], and Sgn [3:0]. The 4-bit Sxn [3:0] and Syn [3:0] values are then fed into the scrambler bit generator. The 4-bit Sgn [3:0] sign values are fed into the sign scrambler nibble generator. (The subscript "n" in these notations is a time index that establishes a temporal relationship between different symbol periods.)
Scrambler bit generator. This function uses the Sxn [3:0] and Syn [3:0] signals along with the tx_mode and tx_enable (transmit enable) signals to generate Scn [7:0], which is further scrambled based on the condition of the tx_mode and tx_enable signals. The tx_mode signal can indicate sending idles (SEND_I), sending zeros (SEND_Z), or sending idles/data (SEND_N). The PCS Data Transmission Enable state machine generates the tx_enable signal, which is either asserted (indicating data transmission is occurring) or not asserted (indicating no data transmission). The 8-bit Scn [7:0] signals are then fed into the data scrambler functional block.
Data scrambler. This function accepts the TXDn [7:0] data from the GMII and scrambles it based primarily on the Scn values and the accompanying control signals. The data scrambler generates the 8-bit Sdn [7:0] value. All eight bits of Sdn [7:0] are passed into the bit-to-symbol quinary symbol mapping block, and two bits, Sdn [7:6], are fed into the convolutional encoder as shown in Figure 5 .
Figure 5. 1000BaseT Convolutional encoder
Convolutional encoder. The encoder uses the Sdn [7:6] bits and tx_enable to generate an additional data bit, which is called Sdn [8]. The clock delayed versions csn-1 [1:0] are passed into the data scrambler functional block. The Sdn [8] bit is then passed into the bit-to-symbol quinary symbol mapping function.
Bit-to-symbol quinary symbol mapping. This function converts the 9-bit Sdn [8:0] data to the appropriate quinary symbols. The function splits the symbols into even and odd subsets, primarily to combat attenuation and noise.
Figure 6a shows a 5x5 constellation of quinary symbols (in reality it is a 5x5x5x5 constellation due to the four-dimensional vector; for simplicity, only a 5x5 constellation is explained). Each point in the 5x5 matrix represents an 8-bit word, which is a vector of four quinary symbols. As the signal propagates on the twisted pairs, the points become less distinct because of noise (see Figure 6b ). A smudged point represents a word affected by noise. Moreover, because the signal attenuates as it travels down the wire, these points become closer (see Figure 6c ). This proximity increases the possibility of interference between neighboring points, which could lead to data corruption. Splitting the symbols into even and odd subsets (Figures 6d and 6e ) increases the distance between the adjacent points, thereby reducing the possibility of data corruption. (Note: An in-depth discussion of the concept of splitting is beyond the scope of this article.)
Figure 6. Graphical effect of splitting symbols into even and odd subsets
The output of this functional block generates the TAn , TBn , TCn , and TDn symbols, which are then passed into the symbol sign scrambler along with the sign scrambled values Sn An , Sn Bn , Sn Cn , and Sn Dn . These generate the required 4D-PAM-5 coded symbols (An , Bn , Cn , and Dn ) that are fed to the PMA.
The PMA block ensures data transmission
The PMA block essentially comprises the signal processing units (see Figure 7 ) to ensure uncorrupted data transmission. Since data transfer occurs over all four pairs, control of echo and crosstalk must be much tighter than with 100 Mbps data transfer.
Figure 7. PMA functional block diagram
Adaptive equalizer. The cable attenuates the higher frequencies more than the lower frequencies, which results in signal distortion. The adaptive equalizer is a digital filter that continually adjusts to minimize the Mean Square Error (MSE) value of the slicer's error signal output. Continuous adaptation of the equalizer coefficients means that the optimum set of coefficients will always be achieved for any given length or quality of cable.
Echo and crosstalk cancellers. The echo and crosstalk cancellers cancel the echo and crosstalk produced during simultaneous transmit and receive. Interference between the transmitted and received signals on the same wire produces echo. Crosstalk is caused when the transmitted signal on each of the other three wire pairs interferes with the received signal on the fourth wire pair. Each of the wire pairs needs an echo and crosstalk canceller.
Automatic gain control (AGC). The automatic gain control acts upon the output of the echo and crosstalk cancellers to adjust the receiver gain.
Baseline wander (BLW) correction. Baseline wander is the slow variation of the direct current (DC) level of the incoming signal. The non-ideal characteristics of the magnetics and the inherent DC component of the transmitted waveform cause this variation. The BLW correction circuit utilizes the slicer error signal to estimate and then correct for BLW.
Slicer. The slicer selects the PAM-5 symbol value {+2, +1, 0, -1, -2} closest to the voltage input value after the signal has been corrected for line Inter Symbol Interference (ISI), attenuation, echo, crosstalk, and BLW. The slicer produces an error output and a symbol value decision output. The error output is the difference between the actual voltage input and the ideal voltage level representing the symbol value. The error output is fed back to the BLW, AGC, crosstalk canceller, and echo canceller blocks to be used in their respective algorithms.
Signaling comparison between 10, 100, and 1000 Mbps Ethernet
Gigabit Ethernet (1000BaseT) uses 4D-PAM-5 coding to transmit and receive data simultaneously on all four unshielded twisted pairs. Because each code word is clocked at 125 MHz, the symbol rate per pair is 125 Mbaud. For data transmitted on all four pairs, the total symbol rate is 500 Mbaud. This rate provides a bandwidth efficiency of 2 bits/baud.
Fast Ethernet (100BaseTX) uses a 4B/5B (4-bit to 5-bit) encoding technique in which a control bit is added to each 4-bit word thereby generating a 5-bit code word. Thus the bandwidth utilization is 0.8 bits/baud.
Ethernet (10BaseT) uses the Manchester coding scheme, which requires twice the bandwidth (20 MHz) and reduces the bandwidth utilization efficiency to 0.5 bits/baud.
This discussion illustrates that 1000 Mbps provides a much higher bandwidth utilization than 10 Mbps and 100 Mbps (see Figure 8 ).
Figure 8. Bandwidth utilization efficiency comparison between 10, 100, and 1000 Mbps Ethernet
1000BaseT offers promising performance
The robust signal processing techniques used in 1000BaseT Ethernet clearly demonstrate the ability of Gigabit Ethernet over copper to emerge as a winner in the Ethernet arena. The powerful signal encoding/decoding and digital filtering enables users to achieve 1000 Mbps Ethernet speed on the same Cat-5 cable currently used for 10 Mbps or 100 Mbps. This promises not only reliable performance, but also a cost-effective solution because the same infrastructure can accommodate traffic at 10 Mbps, 100 Mbps, or 1000 Mbps. Moreover, 1000 Mbps provides four times the bandwidth utilization efficiency achieved by 10 Mbps and more than twice that achieved by 100 Mbps.
Shriram Patwardhan (shriram_patwardhan@dell.com) is a development engineer in the Server Networking and Communications Group at Dell. His work involves qualifying and testing network interface cards for Dell servers. Prior to joining Dell, Shriram was awarded a Texas Telecommunications Engineering Consortium (TxTEC) Fellowship. He has a B.S. in Electrical Engineering from VJTI-University of Mumbai, India, and an M.S. in Electrical Engineering from Texas Tech University.
For more information
Institute of Electrical and Electronics Engineers (IEEE) Std. 802.3-2000 (clause 40): http://www.ieee.org
1000BaseT PCS fundamentals and overview: http://www.iol.unh.edu/training/ge/
National Semiconductor: http://www1.national.com/ds/DP/DP83861.pdf
