Help Me Choose: Memory

 

The new Double Data Rate 3 (DDR3) memory technology offers significant advantages over the previous Double Data Rate 2 Fully Buffered DIMM (DDR2 FBD) technologies:


  • Each CPU has three separate memory controller hubs (MCHs) within the CPU package; memory transactions no longer need to transfer between the CPU and another device to reach RAM.
  • DDR3 memory offers higher bandwidth and lower power consumption compared to the previous DDR2 FBD technologies.

Intel® Xeon® 5500 and 5600 Series processors support two types of DDR3 memory:
  • UDIMMs: Unbuffered Dual Inline Memory Modules
  • RDIMMs: Registered Dual Inline Memory Modules

The register enables RDIMMs to run at higher frequencies and support more DIMMs within a memory channel.

Memory Comparison
UDIMMRDIMM
Registered/BufferedNoYes
Frequencies800, 1,600, 1,333MHz800, 1,600, 1,333MHz
Ranks Supported1 or 21, 2 or 4
Capacity per DIMM1 or 2GB1, 2, 4, 8 or 16GB
Maximum number DIMMs per channel23
Dynamic RAM (DRAM) technologyx8x4 or x8
Temperature SensorYesYes
Error corection code (ECC)YesYes
Single device data correction (SDDC)YesYes
Address ParityNoYes


RDIMMs are a good choice for customers who need:
  • Large memory capacity (up to 16GB DIMMs)
  • Broader future memory expansion roadmap due to the ability to achieve three DIMMs per channel
  • The latest reliability, availability and serviceability (RAS) features (address parity)

UDIMMs are a good choice for customers who need:
  • A limited amount of memory
  • Power and cost savings

Power Considerations
RDIMMs use about one watt of power more per DIMM than comparable UDIMMs due to the register feature. However, the register will allow for performance improvements when the memory is being highly utilized and more than one DIMM per channel is populated. Both UDIMMs and RDIMMs use less power than DDR2 Fully Buffered DIMMs (FBDs).

Speed and Population Dependency
Due to technology limitations, frequency support has some dependency on the DIMMs per channel and the ranks used in a DIMM. For example, one population restriction is that any quad-rank DIMM must be the first DIMM installed in a channel; other than that, the ranks may be mixed.

DIMM TypeDIMM 0DIMM 1DIMM 2Number of DIMMs80010661333
Single-rank (SR)1YesYesYes
Dual-rank (DR)1YesYesYes
UDIMMSRSR2YesYesNo
SRDR2YesYesNo
DRDR2YesYesNo



DIMM TypeDIMM 0DIMM 1DIMM 2Number of DIMMs80010661333
SR1YesYesYes
DR1YesYesYes
Quad-rank (QR)SR2YesYesNo
SRSR2YesYesYes
SRDR2YesYesYes
DRDR2YesYesYes
RDIMMQRSR2YesNoNo
QRDR2YesNoNo
QRQR2YesNoNo
SRSRSR3YesNoNo
SRSRDR3YesNoNo
SRDRDR3YesNoNo
DRDRDR3YesNoNo


Yes:Supported


No:Not Supported



See the Memory Population tab for specific details on how to best populate your system based on memory speed and reliability, availability, serviceability (RAS) features.
Each CPU has three integrated memory controller hubs (MCHs) that have their own memory channel. Memory accesses can be interleaved across the CPU nodes, or the system can be configured in nonuniform memory architecture (NUMA). This is the default BIOS configuration setting from the factory.

Memory Optimized Mode


In this mode, the MCHs run independently of each other; for example, one can be idle, one can be performing a write operation and the other can be preparing for a read operation. Memory may be installed in one, two, or three channels. To fully realize the performance benefit of the memory-optimized mode, all three channels per CPU should be populated.To maximize performance it is better to add dual inline memory modules (DIMMs) across channels before adding more DIMMs to a channel that is already populated.

Maximum Bandwidth Performance

First bank fully populated with DDR3 1,333MHz per MCH
  • Maximum capacity is 48GB. (Capacity of 96GB can be reached with 16GB DIMMs; memory speed will be 1066MHz.)
  • Intel® Xeon® 5550 Series processor or later is required.
  • Two DIMMs per channel will be supported with BIOS Version 1.1.4.

Balanced Performance
First and second banks fully populated with DDR3 1,066MHz per MCH
  • Maximum capacity of 96GB. (Capacity of 192GB can be reached with 16GB DIMMs; memory speed will be 800MHz.)
  • Intel Xeon 5520 Series processor or later is required.
  • Support for 1333MHz for first and second banks is coming soon, and requires Intel Xeon 5550 Series processor or later. (coming soon)

Maximum Capacity

First, second and third banks fully populated with DDR3 800MHz per MCH
  • Maximum capacity is 144GB.
  • Intel Xeon 5500 Series processor or later is required.

Advanced Error Correction Code (ECC) Mode
The reliability, availability and serviceability (RAS)-memory mode uses two MCHs and binds them together to emulate a 128-bit data bus DIMM. This is primarily used to achieve a Single Device Data Correction (SDDC) for DIMMs based on x8 Dynamic RAM (DRAM) technology. SDDC is supported with x4-based DIMMs in every memory mode. One MCH is completely unutilized, and any memory installed in this channel will generate a warning message during POST.

Mirror Mode

This RAS-memory mode uses two of the three channels. Identical data writes are performed on each channel, and reads alternate between the two channels. If excessive memory errors are detected on a channel, that channel is disabled, and the system uses the other channel for future reads and writes. This is essentially a data backup, and enables the system to continue running even during a catastrophic DIMM failure on a channel. Since the memory is copied between DIMMs, the operating system will only see and report half of the installed memory.

Maximum Bandwidth Performance RAS

First bank fully populated with DDR3 1333MHz per MCH (Only 2 MCHs can be utilized)
  • Maximum capacity is 32GB (Capacity of 64GB can be reached with 16GB DIMMs; memory speed will be 1066MHz.) Intel Xeon 5520 Series processor or later is required.
  • Mirror Mode 16GB (Capacity of 32GB can be reached with 16GB DIMMs; memory speed will be 1,066MHz.) Intel Xeon 5520 Series processor or later is required.
  • Intel Xeon 5520 Series processor or later is required.
  • Two DIMMs per channel will be supported with BIOS Version 1.1.4.

Balanced Performance RAS
First and second banks fully populated with DDR3 1,066MHz per MCH (Only 2 MCHs can be utilized)
  • Maximum capacity of 64GB (Capacity of 128GB can be reached with 16GB DIMMs; memory speed will be 800MHz.) Intel Xeon 5520 Series processor or later is required.
  • Mirror Mode 32GB (Capacity of 64GB can be reached with 16GB DIMMs; memory speed will be 1066MHz.) Intel Xeon 5520 Series processor or later is required.
  • Intel Xeon 5520 Series processor or later is required.
  • Support for 1,333MHz for first and second banks requires Intel Xeon 5550 Series processor or later. (coming soon)

Maximum Capacity RAS 
First, second and third banks fully populated with DDR3 800MHz per MCH (Only 2 MCHs can be utilized)
  • Maximum capacity is 96GB.
  • Mirror Mode capacity is 48GB. Intel Xeon 5520 Series processor or later is required.
Selection Criteria
When considering memory options, the five key considerations are price, performance, power, reliability, availability and serviceability (RAS) features, and scalability.
  • Performance = RDIMM
  • Power = UDIMM
  • RAS features = RDIMM
  • Scalability = RDIMM
  • Price = UDIMM

Memory Performance
Memory performance is affected by CPU speed, memory ranks and DIMMs per channel.
  • Dual Data Rate 3 (DDR3) 1,333MHz is only supported in one Dula Inline Memory Module (DIMM) per channel per memory contyroller hub (MCH); two DIMMs per channel will be supported with BIOS version 1.1.4.
  • DDR3 1,066MHz is only supported in two DIMMs per channel per MCH; when third DIMM is populated, memory speed will clock down to 800MHz.
  • Maximum capacity memory speed is 800MHz.

For maximum memory performance:
  • Use DDR3 1333MHz memory across all three channels per CPU.
  • This speed can only support one DIMM per channel and thus, a maximum of three DIMMs per CPU; two DIMMs per channel will be supported with BIOS version 1.1.4.
  • No quad-rank DIMMs can be used

For balanced memory performance:
  • Use DDR3 1,066MHz memory across all three channels per CPU.
  • This speed can only support two DIMMs per channel, and thus a maximum of six DIMMs per CPU.

For maximum memory capacity:
  • Use DDR3 800MHz memory across all three channels per CPU.
  • This speed will support three DIMMs per channel and thus, a maximum of nine DIMMs per CPU.
Address Parity
The ability to detect an error on a single address line. This is not correctable.

Advanced ECC Mode
This mode uses two MCHs and ties them together to emulate a 128-bit data bus DIMM. This is primarily used to achieve a Single Device Data Correction (SDDC) for DIMMs based on x8 DRAM technology. SDDC is supported with x4 based DIMMs in every memory mode. One MCH is completely not utilized, and any memory installed in this channel will generate a warning message during POST.

DDR3
Double Data Rate 3, memory technology.

DIMM
Dual Inline Memory Module. This is the memory stick that is installed in each memory slot. It is composed of multiple memory chips and, in some cases, registers, buffers and/or temperature sensors.

ECC
This mode uses two MCHs and ties them together to emulate a 128-bit data bus DIMM. This is primarily used to achieve a Single Device Data Correction (SDDC) for DIMMs based on x8 DRAM technology. SDDC is supported with x4-based DIMMs in every memory mode. One MCH is completely not utilized, and any memory installed in this channel will generate a warning message during POST.

MCH
Memory Controller Hub.

Memory Optimized Mode
In this mode, the MCHs run independently of each other; for example, one can be idle, one can be performing a write operation, and the other can be preparing for a read operation. Memory can be installed in one, two, or three channels. To fully realize the performance benefit of the memory-optimized mode, all three channels per CPU should be populated. This implies that some "atypical" memory configurations, such as 3GB, 6GB or 12GB, will yield the best performance. This memory-optimized mode is the recommended mode unless specific RAS features are needed.

Mirror Mode
One of the RAS-memory modes is mirror mode. This mode uses two of the three channels. Identical data writes are performed on each channel, and reads alternate between the two channels. If excessive memory errors are detected on a channel, then that channel is disabled and the system uses the other channel for future reads and writes. This is essentially a data backup, and enables the system to continue running even during a catastrophic DIMM failure on a channel. Since the memory is copied between DIMMs, the operating system will only see and report half of the installed memory.

Mirroring
The memory controller is configured to allow the same data to be written to two banks of DIMMs. Each bank's data is identical to the other; in this way, if one bank fails or has multiple bit errors, there is a backup data bank. The OS will report half of your installed memory.

Rank
Number of 64-bit wide data areas.

RAS
Reliability, Availability and Serviceability.

SDDC
Memory systems that utilize Single Device Data Correction can detect and correct multibit errors that come from a single memory chip on the DIMM.

Temperature Sensors
All DIMMs have integrated temperature sensors. This feature enables the server to monitor for over-temperature conditions with the resolution of individual DIMMs and can provide more efficient thermal and power management.