Help Me Choose: Memory

 

The new Double Data Rate 3 (DDR3) memory technology offers significant advantages over the previous Double Data Rate 2 (DDR2) Fully Buffered DIMM (FBD) technologies:

  • Each CPU has an integrated memory controller within the CPU package; memory transactions no longer need to transfer between the CPU and another device to reach RAM.
  • DDR3 memory offers higher bandwidth and lower power consumption compared to the previous DDR2 FBD technologies.

Intel® Xeon® 3400 Series processors support two types of DDR3 memory:
  • UDIMMs: Unbuffered Dual Inline Memory Modules
  • RDIMMs: Registered Dual Inline Memory Modules
The register enables RDIMMs to run at higher frequencies and support more DIMMs within a memory channel.

Memory Comparison
UDIMMRDIMM
Registered/BufferedNoYes
Frequencies800, 1066, 1,333MHz800, 1066, 1,333MHz
Ranks Supported1 or 21, 2 or 4
Capacity per DIMM1, 2 and 4GB1, 2, 4 or 8GB
Maximum number DIMMs per channel23
Dynamic RAM (DRAM) technologyx8x8
Temperature SensorYesYes
Error Correction Code (ECC)YesYes
Single Device Disable Code (SDDC)YesYes
Address ParityNoYes

RDIMMs are a good choice for customers who need:
  • Large memory capacity
  • Broader future memory expansion road map due to the ability to achieve three DIMMs per channel

UDIMMs are a good choice for customers who need:
  • A limited amount of memory
  • Power and cost savings

Power Considerations
RDIMMs use about 1W of power more per DIMM than comparable UDIMMs due to the register feature. However, the register will allow for performance improvements when the memory is highly utilized and more than one DIMM per channel is populated. Both UDIMMs and RDIMMs use less power than DDR2 FBDs.

Speed and Population Dependency
Due to technology limitations, frequency support has some dependency on the DIMMs per channel and the ranks used in a DIMM. For example, one population restriction is that any quad-rank DIMM should always be populated in the far slot in this combination. Other than that, the ranks may be mixed.

DIMM TypeDIMM 0DIMM 1DIMM 2Number of DIMMs80010661333
Single-rank (SR)1YesYesYes
Dual-rank (DR)1YesYesYes
UDIMMSRSR2YesYesYes
DRSR2YesYesYes
DRDR2YesYesYes

DIMM TypeDIMM 0DIMM 1DIMM 2Number of DIMMs80010661333
SR1YesYesYes
DR1YesYesYes
Quad-rank (QR)2YesYesNo
SRSR2YesYesYes
DRSR2YesYesYes
DRDR2YesYesYes
RDIMMQRSR2YesNoNo
QRDR2YesNoNo
QRQR2YesNoNo
SRSRSR3YesNoNo
DRSRSR3YesNoNo
DRDRSR3YesNoNo
DRDRDR3YesNoNo

Yes: Supported

No: Not Supported
Each CPU has an integrated memory controller within the CPU package with two memory channels.

Maximum Bandwidth Performance
  • First bank fully populated with DDR3 1,333MHz per memory controller hub (MCH)
  • Maximum bandwidth performance at 16GB
  • Must have Intel® Xeon® 3430 Series processor and up

Maximum Capacity

  • First, second and/or third banks fully populated
  • Maximum capacity 32GB (Dell™ PowerEdge™ T310) with DDR3 800MHz per MCH
  • Maximum capacity 16GB (PowerEdge T110 and R210) with DDR3 1,333MHz per MCH
  • Must have Intel Xeon 3430 Series processor and up

Balanced Performance
  • First and second banks fully populated with DDR3 1,066Mhz per MCH
  • Balance performance at 16GB (PowerEdge T110 and R210)
  • Balance performance at 32GB (PowerEdge T310), however memory speed will drop to 800MHz per MCH
  • Must have Intel Xeon 3430 Series processor and up




Selection Criteria
When considering memory options, the three key considerations are price, reliability and power.
  • Reliability = RDIMM
  • Power = UDIMM
  • Price = UDIMM

Memory Restriction

Unbuffered DDR3 Error Correction Code

  • Supports up to two DIMMs per channel; two channels supported per processor
  • Maximum capacity memory speed is 1,333MHz
  • Core™ i3 530 and 540, Pentium® G6950, Celeron® G1101 and Xeon® LV3406 processors support unbuffered DDR3 memory only.
  • Pentium G6950, Celeron G1101 and Xeon LV3406 will support up to 1,066MHz unbuffered DDR3 memory only.

Registered DDR3 ECC
  • Supports up to three DIMMs per channel, two channels supported per processor
  • Maximum speed for quad-rank memory is 1,066MHz; when second quad-rank DIMM is populated, memory speed will clock down to 800MHz.
  • Maximum capacity memory speed is 800MHz.
Address Parity
The ability to detect an error on a single address line. This is not correctable.

Advanced Error Correction Code (ECC) Mode
This mode uses two memory controller hubs (MCHs) and ties them together to emulate a 128-bit data bus DIMM. This is primarily used to achieve a single device data correction (SDDC) for DIMMs based on x8 dynamic RAM (DRAM) technology. SDDC is supported with x4 based DIMMs in every memory mode. One MCH is completely unutilized and any memory installed in this channel will generate a warning message during POST.

DDR3
Double Data Rate 3, memory technology.

DIMM
Dual Inline Memory Module. This is the memory stick that is installed in each memory slot. It is composed of multiple memory chips and, in some cases, registers, buffers and/or temperature sensors.

ECC
This mode uses two MCHs and ties them together to emulate a 128-bit data bus DIMM. This is primarily used to achieve a SDDC for DIMMs based on x8 DRAM technology. SDDC is supported with x4-based DIMMs in every memory mode. One MCH is completely unutilized, and any memory installed in this channel will generate a warning message during POST.

MCH
Memory Controller Hub

Memory Optimized Mode
In this mode, the MCHs run independently of each other; for example, one can be idle, one can be performing a write operation and the other can be preparing for a read operation. Memory may be installed in one, two or three channels. To fully realize the performance benefit of the memory optimized mode, all three channels per CPU should be populated. This implies that some atypical memory configurations, such as 3, 6, or 12GB, will yield the best performance. The memory optimized mode is recommended unless specific RAS features are needed.

Mirror Mode
One of the RAS-memory modes is mirror mode. This mode uses two of the three channels. Identical data writes are performed on each channel, and reads alternate between the two channels. If excessive memory errors are detected on a channel, then that channel is disabled and the system uses the other channel for future reads and writes. This is essentially a data backup and enables the system to continue running even during a catastrophic DIMM failure on a channel. Since the memory is copied between DIMMs, the operating system will only see and report half of the installed memory.

Mirroring
The memory controller is configured to allow the same data to be written to two banks of DIMMs. Each bank's data is identical to the other; consequently, if one bank fails or has multiple bit errors, there is a backup data bank. The OS will report half of your installed memory.

Rank
Number of 64-bit wide data areas

RAS
Reliability, availability and serviceability

SDDC
Memory systems that utilize single device data correction can detect and correct multibit errors that come from a single memory chip on the DIMM.

Temperature Sensors
All DIMMs have integrated temperature sensors. This feature enables the server to monitor for over temperature conditions with the resolution of individual DIMMs. This can provide more efficient thermal and power management.