I try to build the asymmetric memory environment for our DELL servers (e.g., Dell-R720 with 2-socket, 4-channel/socket)
Actually, I want to control differnet I/O frequency and access latency for each DRAM channel In this case, my questions is below.
1. Is it possible to control different frequency and access latency for each DRAM channel?
2. can I control DRAM timing parameter from the CSR registers?
I have found the CSR registers and changed it for asymmetric memory access (e.g., T_RP, T_CL), but I'm not sure if it work well. 3. Also, I wonder how to control CSR register values with RW_LB attribute.
In this case, Do you have any suggestions?