I'm not finding the "official" definition quickly so here is a basic answer and we can flesh it out later. This answer will be based on the older (pre VMAX3 to VMAX3) version of cycle switching. For VMAX3 to VMAX3 (or newer) it works slightly different, but I'll talk about that at the end.
With SRDF/A (specifically in asynchronous mode) everything runs in cycles. When you first flip to async mode it all starts with the first cycle to gather data that changes on the source device(s). The array tracks the changes to the source for a period of time defined by the minimum cycle time. This used to be 30 seconds, but the default on newer arrays is 15 seconds. After the minimum cycle time is up the first cycle switch happens. It should be noted that this is the only one that is easily predictable as from here on out the cycle switch will be dependant on multiple things happening.
So, at the first cycle switch the first cycle (set) of changes begins transferring over the link to the remote array. At the same time the source array starts collecting a new cycle of data changes on the source. The second cycle switch is still dependant on the minimum cycle time completing, but it is ALSO dependant on the transfer cycle in flight completing and being acknowledged by the remote array. Once BOTH of these conditions have been met the second cycle switch occurs. So if the transfer to the remote array is slow the second cycle can gather changes for more than the minimum cycle time.
Once the second cycle switch triggers we again start a new data change gathering cycle on the source volume(s), we start transferring the second cycle data to the remote array, and we also start de-staging the data from the very first cycle which is now sitting on the target array but hasn't been written to disk yet. This time around we are finally up to "full speed" and the third cycle switch (and every one after it) requires meeting three criteria: The minimum cycle time must expire, the transfer cycle between arrays must complete, and the destage of the cycle on the target array to disk must complete. Any delay in the transfer or the write to disk can extend the cycle time beyond the minimum.
At this point each cycle switch acts the same requiring all three criteria to be met to switch everything to the next cycle.
There is a bit of a variation of this for VMAX3 arrays (and newer) at both the source and target end of a link. I haven't worked with this configuration yet, but if I'm remembering correctly the cycle time is fixed for the gather cycles on the source array and a delay in one of the other stages will have the source array queue up cycles to be transmitted in order as soon as they can be to help catch up from a temporary backlog. This helps alleviate an issue where the older configuration could get so far behind if something slowed down the transmit or destaging cycles that it could never catch up properly in async mode.
If anyone has more detail on this last part, please feel free to chime in as I'm less familiar with the newer SRDF/A cycle switching since I've never actually "lived" it.
To go back and make a very long answer short though... a cycle switch is the "trigger" between cycles when all the required criteria have been met.
Thanks for the reply.
So as I understand it in a nutshell, the "first" switch takes place after the rdf/a session's first gather cycle. The next gather cycle begins the next cycle set which in addition to 1st cycle set (in flight) is dependent on target's "ack" from the 1st cycle and the remote de-staging of 1st cycle set to reach the 2nd switch (full speed?). Where in the process continues with subsequent switches triggered by target acks. The max outstanding switches allow for up to 2 switches. Am I close?
Close, yes 🙂
First off the second cycle switch is not dependant on the destaging, just the "ack" from the transfer. The third cycle switch adds in a dependency on the destaging.
And there aren't "outstanding switches"... each cycle switch triggers all cycles to switch at the same time to the next cycle. So at any point in time, once things get moving, there is always a data gathering cycle, a transfer cycle, and a destage cycle happening simultaneously.
Years ago I saw a really good diagram of this that helps it make more sense, but I can't seem to find a copy online right now. I think it's in my Information Storage And Management book which is sitting at home by my bedside. I'll see if I can dig up that diagram tonight and produce a likely facsimile.
Maybe a better way of narrowing it down though would be to say that the "cycle switch" isn't a "thing" but an event. it coordinates the timing of the various cycles across the entire process.
Got a quick unrelated question. Is Volume Set Address flag analogous to Dynamic LUN addressing in prior VMAX? I see it's a dirport flag, but can't find it's definition.
Sorry, I don't know this one off the top of my head and I haven't had a chance to dig in to confirm the answer. I vaguely remember this changing how some systems see the HLU but I can't remember the details right now. I know that historically it mattered for some Open Systems hosts but not for others.
I'll see what I can find in the next few days (if no one else has a better answer before then)