I have a question regarding VMAX cache slot destaging. I am reading Symmetrix Performance Workshop Student guide 012110 - Symmetrix Cache My question is, what are the rules outside of Write Miss for cache destaging. The reason I am asking is the description of Sequential Read with Prefetch indicates that the cache is filled with pre-fetched data, what is the algorithm used to determine which slot to sacrifice for pre-fetch use or delayed fast writes ?
To the extent I know, there is an LRU mechanism, which destages the least recently used cache slots to accommodate the incoming data or prefetched data. LRU is an algorithm designed to chose which data should be eliminated when emory becomes full. The principle here assumes that because it is least recently used, it will not be needed again soon.