Toshiba B01A for model number(s) KPM5XRUG480G, KPM5XRUG960G, KPM5XRUG1T92, KPM5XRUG3T84, KPM5XRUG7T68, KPM5XVUG400G, KPM5XVUG480G, KPM5XVUG800G, KPM5XVUG960G, KPM5XVUG1T60, KPM5XVUG1T92, KPM5XVUG3T20, KPM5XVUG3T84, KPM5XVUG7T68, KPM5XMUG400G, KPM5XMUG800G, and KPM5XMUG1T60, KPM5XMUG3T20.

Fixes:
-Apply the solution developed for PM4 to the PM5. Refresh the SRAM data located inside the Flash when L3 data recovery is invoked.
-When the FTL table rebuild from a page in a block is completed, if the blocks which FTL rebuild was completed are selected to execute GC, the F/W detects uncertain value in the pointer to address the next GC target, and assert condition happens. The fix F/W is to set up the next GC target at the appropriate timing.
-There was a small window to prevent the drive PLP operation due to the internal read process for host Read command execution. When the sudden power-off is detected, terminate the internal read process and execute the PLP to complete FTL data saving to the Flash.
-Adjust the Random Write performance of 9W and 12W to meet the design spec.
-Report appropriate values for 6Gbps.
RECEIVER EQUALIZATION GAIN CONTROL = 02h
RECEIVER BOOST CONTROL = 03h
-The fix F/W is to recognizes these two internal signals correctly and switch the block for saving delta to keep the host write operation.
-Modify the FW routine to prevent accessing the invalid memory at L3 data recovery.
-Decrease the number of blocks that can be registered in the GC control table not to get the control table full.
-Shorten the FW overhead to reduce the L3 data recovery execution time.
-Vth Tracking and FSB error recovery are introduced in order to improve data recovery capability for read process.
-ModePage 0Ah reports Foreground extend self-test time.
-Modify firmware to correctly judge the garbage collection source block supply status to avoid the endless invalid data (All 0) writing.

Enhancements:
-n/a