Dell EMC PowerEdge M640 Installation and Service Manual
Memory mirroring
Memory mirroring offers the strongest memory module reliability mode, providing improved uncorrectable multi-bit failure protection. In a mirrored configuration, the total available system memory is one half of the total installed physical memory. Half of the installed memory is used to mirror the active memory modules. In the event of an uncorrectable error, the system switches over to the mirrored copy. This ensures Single Device Data Correction (SDDC) and multi-bit protection.
The installation guidelines for memory modules are as follows:
- Memory modules must be identical in size, speed, and technology.
- Memory modules must be populated in sets of 6 per CPU to enable memory mirroring.
| Processor | Configuration | Memory population | Memory population information |
|---|---|---|---|
| Single CPU | Optimized (Independent channel) population order | 1, 2, 3, 4, 5, 6, 7, 8 | Odd amount of DIMMs per CPU allowed. |
| Mirroring population order | {1, 2, 3, 4, 5, 6} | Mirroring is supported with 6 DIMMs per CPU | |
| Single rank sparing population order | 1, 2, 3, 4, 5, 6, 7, 8 | Populate in this order, odd amount per CPU allowed. Requires two ranks or more per channel. | |
| Multi rank spare population order | 1, 2, 3, 4, 5, 6, 7, 8 | Populate in this order, odd amount per CPU allowed. Requires three ranks or more per channel. | |
| Fault resilient population order | {1, 2, 3, 4, 5, 6} | Supported with 6 DIMMs per CPU. | |
| Dual CPU (Start with CPU1. CPU1 and CPU 2 population should match) | Optimized (Independent channel) population order | C1{1},C2{1},C1{2},C2{2},C1{3},C2{3}… | Odd amount of DIMMs per CPU allowed. |
| Mirroring population order | C1{1,2,3,4,5,6},C2{1,2,3,4,5,6} | Mirroring is supported with 6 DIMMs per CPU. | |
| Single rank sparing population order | C1{1},C2{1},C1{2},C2{2},C1{3},C2{3}… | Populate in this order, odd amount per CPU allowed. Requires two ranks or more per channel. | |
| Multi rank spare population order | C1{1},C2{1},C1{2},C2{2},C1{3},C2{3}… | Populate in this order, odd amount per CPU allowed. Requires three ranks or more per channel. | |
| Fault resilient population order | C1{1,2,3,4,5,6},C2{1,2,3,4,5,6} | Supported with 6 DIMMs per CPU. |
Please provide ratings (1-5 stars).
Please provide ratings (1-5 stars).
Please provide ratings (1-5 stars).
Please select whether the article was helpful or not.
Comments cannot contain these special characters: <>()\