Dell EMC OpenManage Command Line Interface Guide Version 9.1


Capabilities and cache properties of a specific processor

To view the cache properties of a processor on a given connector, type:
omreport chassis processors index=n
omreport mainsystem processors index=n

The index parameter is optional. If you do not specify the index, Server Administrator displays properties for all processors. If you specify the index, Server Administrator displays properties for a specific processor.

The following table lists the fields that are defined for the capabilities present on a particular microprocessor:

Table 1. Microprocessors and Fields . This table lists the Microprocessors and Fields
Microprocessor Fields
Intel Processor
  • 64-bit Support
  • Hyperthreading (HT)
  • Virtualization Technology (VT)
  • Demand-Based Switching (DBS)
  • Execute Disable (XD)
  • Turbo Mode
AMD Processor
  • 64-bit Support
  • AMD-V
  • AMD PowerNow!
  • No Execute (NX)
The following fields are defined for a cache present on a particular microprocessor. If the cache is internal to the processor, the fields do not appear in the cache report:
  • Speed
  • Cache Device Supported Type
  • Cache Device Current Type
  • External Socket Name

The following table displays the fields that are displayed for each cache on a particular processor:

Table 2. Fields And Description. This table lists the Fields And Description
Field Description
Status Reports whether a specific cache on the processor is enabled or disabled.
Level Refers to a primary or secondary cache. Primary-level cache is a memory bank built into the processor. Secondary-level cache is a staging area that feeds the primary cache. A secondary-level cache is built into the processor or resides in a memory chipset outside the processor. The internal processor cache is referred to as a Level 1 (or L1). L2 cache is the external cache in a system with an Intel Pentium processor, and it is the second level of cache that is accessed. The names L1 and L2 are not indicative of where the cache is physically located (internal or external), but describe which cache is accessed first (L1, therefore internal).
Speed Refers to the rate at which the cache can forward data from the main memory to the processor.
Max Size Maximum amount of memory that the cache can hold in kilobytes.
Installed Size Actual size of the cache.
Type Indicates whether the cache is primary or secondary.
Location Location of the cache on the processor or on a chipset outside the processor.
Write Policy

Describes how the cache deals with a write cycle. In a write-back policy, the cache acts like a buffer. When the processor starts a write cycle, the cache receives the data and stops the cycle. The cache then writes the data back to the main memory when the system bus is available.

In a write-through policy, the processor writes through the cache to the main memory. The write cycle does not complete until the data is stored into the main memory.

Refers to the way in which main memory content is stored on the cache.
  • A fully associative cache allows any line in main memory to store at any location in the cache.
  • A n-way set-associative cache directly maps n specific lines of memory to the same n lines of cache. For example, line 0 of any page in memory is stored in line 0 of cache memory.
Cache Device Supported Type Type of static random access memory (SRAM) that the device can support.
Cache Device Current Type Type of the currently installed SRAM that the cache is supporting.
External Socket Name Silk Screen Name Name printed on the system board next to the socket.
Error Correction Type Identifies the type of error checking and correction (ECC) that this memory can perform. Examples are correctable ECC or uncorrectable ECC.

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