I have a question regarding VMAX cache slot destaging. I am reading Symmetrix Performance Workshop Student guide 012110  - Symmetrix Cache My question is, what are the rules outside of Write Miss for cache destaging. The reason I am asking is the description of Sequential Read with Prefetch indicates that the cache is filled with pre-fetched data, what is the algorithm used to determine which slot to sacrifice for pre-fetch use or delayed  fast writes ?