In the eight-bay
chassis that supports up to eight quarter-width compute sleds, a compute
sled is mapped to a single port on each I/O module.Figure 1. I/O module port
mapping—eight-bay chassis
The following table lists
the compute sleds and the ports to which they are mapped.
Table 1. I/O module port
mapping in eight-bay chassisIn an eight-bay chassis, the quarter-width compute
sled populated in bay 1a is mapped to port 1 on both IO Module A1
(Top) and IO Module A2 (Bottom). In an eight-bay chassis, the quarter-width
compute sled populated in bay 1b is mapped to port 2 on both IO Module
A1 (Top) and IO Module A2 (Bottom). In an eight-bay chassis, the
quarter-width compute sled populated in bay 1c is mapped to port 3
on both IO Module A1 (Top) and IO Module A2 (Bottom). In an eight-bay
chassis, the quarter-width compute sled populated in bay 1d is mapped
to port 4 on both IO Module A1 (Top) and IO Module A2 (Bottom). In
an eight-bay chassis, the quarter-width compute sled populated in
bay 3a is mapped to port 5 on both IO Module A1 (Top) and IO Module
A2 (Bottom). In an eight-bay chassis, the quarter-width compute sled
populated in bay 3b is mapped to port 6 on both IO Module A1 (Top)
and IO Module A2 (Bottom). In an eight-bay chassis, the quarter-width
compute sled populated in bay 3c is mapped to port 7 on both IO Module
A1 (Top) and IO Module A2 (Bottom). In an eight-bay chassis, the
quarter-width compute sled populated in bay 3d is mapped to port 8
on both IO Module A1 (Top) and IO Module A2 (Bottom).
Compute sled
IO Module A1 (Top)
IO Module A2 (Bottom)
1a
1
1
1b
2
2
1c
3
3
1d
4
4
3a
5
5
3b
6
6
3c
7
7
3d
8
8
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