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chiodp
149 Posts
0
August 21st, 2008 07:00
gauge1
17 Posts
August 21st, 2008 11:00
RRR
4 Operator
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5.7K Posts
August 22nd, 2008 10:00
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chiodp
149 Posts
0
August 21st, 2008 07:00
Note the speed of CX4 processor is less but are quad core , the number of transaction they can perform are more than double compare with the dual core .
CX3-80
CX3-40f
CX3-40
CX3-40c
CX3-20f
CX3-20
CX3-20c
CX3-10c
Disks
480
240
240
240
120
120
120
60
Enclosures
32
16
16
16
8
8
8
4
SPs
2
2
2
2
2
2
2
2
CPU/SP
2x3.6GHz
2x2.8GHz
2x2.8GHz
2x2.8GHz
1x2.8GHz
1x2.8GHz
1x2.8GHz
1x1.8GHz
FC FE/SP
4@4Gb
4@4Gb
2@4Gb
2@4Gb
6@4Gb
2@4Gb
2@4Gb
2@4Gb
iSCSI FE/SP
-
-
-
4@1Gb
-
-
4@1Gb
2@1Gb
BE/SP
4@4Gb
4@4Gb
2@4Gb
2@4Gb
1@4Gb
1@4Gb
1@4Gb
1@4Gb
System Mem
16GB
8GB
8GB
8GB
4GB
4GB
4GB
2GB
Cache
6728MB
3016MB
3016MB
3016MB
1053MB
1053MB
1053MB
310MB
W Cache
3072MB
2500MB
2500MB
2500MB
1053MB
1053MB
1053MB
310MB
HA Hosts [ha1]
256
128
128
128
128
128
128
64
Min Size
9U
5U
5U
5U
5U
5U
5U
5U
LUNs
2048
2048
2048
2048
1024
1024
1024
512
RGs
240
120
120
120
60
60
60
30
LUNs/RG
128
128
128
128
128
128
128
128
SGs
512
256
256
256
256
256
256
128
LUNs/SG
256
256
256
256
256
256
256
256
CMI
PCIe x8
PCIe x4
PCIe x4
PCIe x4
PCIe x4
PCIe x4
PCIe x4
PCIe x4
Rsrvd LUNs
512
256
256
256
128
128
128
64
Message was edited by:
chiodp
gauge1
17 Posts
0
August 21st, 2008 11:00
RRR
4 Operator
•
5.7K Posts
0
August 22nd, 2008 10:00
If you include [code ] and [/code ] around your ascii txt, the layout is maintained.... (hint)