SPS and write cache

Question

We had a issue where a Dr array that we mirror too had a failed SPS. This produced Alerts stating that the write cache was disabled. Prior to replacing the SPS we had serveral remote mirrors go in and out of sync. I suspected that this would happen but i was told by our supplier that the write cache does not disable.
I ran some Cli against the SP and infact it said that the cache remained enabled.

I am a little confused and would like to hear other points of view

kelleg · Accepted Answer

In the Navisphere display, if you right-click on SPA and select View Events, you will see a complete list of all the events on the array. Somewhere in the list will be the original error that you received with the time stamp - by reviewing the sequence of the error, the replacement of the SPS-A, the cache disabling and the mirror errors you should be able to determine when each event occurred - with the Write cache disabled it is possible that this introduced a time delay on the sync for the mirrors.

glen

DGM3 · Answer

It would help if you could clarify what type of arrays were involved (e.g. CX-series or CX3-series or CX4-series).Thanks,DGM

sidanat · Answer

Cx700 flare 24

DGM3 · Answer

On a CX700, the failure of a single SPS unit (failure meaning, it no longer is holding charge properly) will not cause the write cache to disable, as the CX700 has dual SPS units (this is assuming that the other SPS unit is still functioning correctly). Write caching requires at least one SPS unit to be fully charged.

That said, when someone goes to physically replace the failed SPS unit - the act of disconnecting the it from the array is going to temporarily result in a power supply in the CX700's base enclosures (where the Storage Processors and first tray of drives are) losing AC input - that will disable write cache, until the new SPS unit is connected (thus restoring AC input).

Or said another way - on a CX700 a single SPS unit failing-to-hold charge won't cause write cache to disable, but interrupting AC input (such as during maintenance activity) to a power supply "behind" an SPS unit will cause write cache to disable.

Does that info help explain what was observed?

Regards,
DGM

sidanat · Answer

Excellent insight.Looking at the alerts we received it seems that the array considered that the SPS had been removed therefore the write cache was disabled. See below'Device Enclosure 0 SPS ADescription The UPS failed or the UPS serial cable to the storage system is not connected. Write cache was disabled and will remain disabled until you repair the UPS. See the AX-series documentation for replacement instructions.'That would then fit in as far as the mirrors going in and out of sync ?but the odd thing when i ran the naviseccli getall -sp this reported that the R/W cache was indeed enabled.So i was getting conflicting output from the Array?

CLARiiON

SPS and write cache

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