Dell chat and Phone sales wouldn't have this nor would any other vendor.
DPL Prefetch and L2 Streaming Prefetch settings are not configurable in bios.
This instruction must be executed at privilege level 0 or in real-address mode; otherwise, a general protection exception #GP(0) will be generated. Specifying a reserved or unimplemented MSR address in ECX will also cause a general protection exception.
I'm a bit confused. Other vendors (including Dell's Enterprise sales side) do provide exactly this information.
I didn't understand the point you were making about the MSR registers. As you point out at the bottom, there is no MSR based way to disable prefetching in Haswell.
There is, however, a BIOS based way. The BIOS ways are distinct from the MSR based ways (the BIOS does not use the MSR to disable this functionality). Many systems from Nehalem and onwards *do* offer BIOS based ways to disable at least some of the prefetchers, and I'm curious curious if the XPS 8700 is one of them.
Your screenshot shows a system which can disable the L2 adjacent line fetcher and one other "unspecified" prefetcher, which is *probably* the L2 streamer. Did it come from the XPS line or some other dell?
Screen Shot Did NOT come from a Retail Consumer Machine or a Dell. Nelahem came before haswell by several years. Normal consumers do not need to change this in processors. "Intel has not disclosed how to disable the prefetchers on processors from Nehalem onward."
speedstep
9 Legend
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47K Posts
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September 9th, 2014 08:00
Dell chat and Phone sales wouldn't have this nor would any other vendor.
DPL Prefetch and L2 Streaming Prefetch settings are not configurable in bios.
This instruction must be executed at privilege level 0 or in real-address mode;
otherwise, a general protection exception #GP(0) will be generated.
Specifying a reserved or unimplemented MSR address in
ECX will also cause a general protection exception.
In Linux you can enable or disable the hardware prefetchers using msr-tools http://www.kernel.org/pub/linux/utils/cpu/msr-tools/.
The following enables the hardware prefetcher (by unsetting bit 9):
[root@... msr-tools-1.2]# ./wrmsr -p 0 0x1a0 0x60628e2089 [root@... msr-tools-1.2]# ./rdmsr 0x1a00x60628e2089The following disables the hardware prefetcher (by enabling bit 9):
[root@... msr-tools-1.2]# ./wrmsr -p 0 0x1a0 0x60628e2289 [root@... msr-tools-1.2]# ./rdmsr 0x1a00x60628e2289Programatically, you can do this as root by opening
/dev/cpu//msr and using pwrite to write to the msr "file" at the0x1a0offset.However according to INTEL:
"Intel has not disclosed how to disable the prefetchers on processors from Nehalem onward.
You'll need to disable the prefetchers using options in the BIOS."
This is not a feature that is offered on ANY DELL system AFAIKT.
If its there it looks like this. Hardware Prefetcher and Adjacent Cache Line.
1 = Disable
1 = Disable
BeeOnRope
1 Rookie
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September 9th, 2014 21:00
Thanks for your reply.
I'm a bit confused. Other vendors (including Dell's Enterprise sales side) do provide exactly this information.
I didn't understand the point you were making about the MSR registers. As you point out at the bottom, there is no MSR based way to disable prefetching in Haswell.
There is, however, a BIOS based way. The BIOS ways are distinct from the MSR based ways (the BIOS does not use the MSR to disable this functionality). Many systems from Nehalem and onwards *do* offer BIOS based ways to disable at least some of the prefetchers, and I'm curious curious if the XPS 8700 is one of them.
Your screenshot shows a system which can disable the L2 adjacent line fetcher and one other "unspecified" prefetcher, which is *probably* the L2 streamer. Did it come from the XPS line or some other dell?
Thanks in advance for your response.
speedstep
9 Legend
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47K Posts
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September 10th, 2014 07:00
Screen Shot Did NOT come from a Retail Consumer Machine or a Dell. Nelahem came before haswell by several years. Normal consumers do not need to change this in processors. "Intel has not disclosed how to disable the prefetchers on processors from Nehalem onward."