Hi Hollow_Beam,

While researching on the issue, I found that most of the people facing this issue are trying to install the Windows 8 Customer Preview as this error occurs only in the Release Preview.  

You can also try the following workaround or test the Windows 8 Consumer Preview.

Download the ISO(Windows 8 Release Preview) and burn it to a DVD or create a bootable USB flash drive.  Boot from the media that you created. If your CPU does not support NX you will see a code 5D blue screen before setup starts. This is rare, but if it happens, then Windows 8 could not be started.

This workaround may succeed because Windows contains two installers:

1. The End User Installer (setup.exe at the root of the Windows DVD)
2. The Commercial Installer (setup.exe found in the \sources directory of the Windows DVD).

The commercial installer runs when the PC is booted from DVD/USB media and does not perform the NX/SSE2 checks and attempts to enable NX/SSE2 on supported systems.  

You can also visit the following link for further information on this issue and the workaround:
http://bit.ly/L7frRh

I hope you find this information useful.

Thanks, but an Intel Core2Duo E8500 have NX feature, I really think it's a Bios problem.

Like I said, I have tried to install it, and 5D error screen appear.

I test many other software, they all saying the same : NX feature not enable.

Problem, I've enabled it in BIOS (Security).

Hi Hollow_Beam,

You can use the Sysinternals tool “Coreinfo” to determine the features that your CPU supports. It is available for download from TechNet at the following link:
technet.microsoft.com/.../cc835722

You can also install the Consumer Review on your computer instead of Release Preview.

I hope this information is helpful. Please reply to this message if you need further information.

Hi Rajath,

Thanks, I've used Coreinfo, it confirm that my proc supports no-execute page protection, but the BIOS of my Optiplex don't enable the feature (I've the feature in it).

I'm very disappointed, it's a BIOS bug and I think Dell will never correct it...

Hi Hollow_Beam,

Thank you for replying and I am sorry to know about that. Please post the result that is displayed by the “Coreinfo” software so that we can forward it to the appropriate team.

Hi Rajath,

Thanks to take care of my case. ^^

Optiplex 755 - Coreinfo :

Intel(R) Core(TM)2 Duo CPU     E8500  @ 3.16GHz

x86 Family 6 Model 23 Stepping 6, GenuineIntel

HTT       * Hyperthreading enabled

HYPERVISOR - Hypervisor is present

VMX       * Supports Intel hardware-assisted virtualization

SVM       - Supports AMD hardware-assisted virtualization

EM64T     * Supports 64-bit mode

SMX       * Supports Intel trusted execution

SKINIT     - Supports AMD SKINIT

EIST       * Supports Enhanced Intel Speedstep

NX         * Supports no-execute page protection

PAGE1GB   - Supports 1 GB large pages

PAE       * Supports > 32-bit physical addresses

PAT       * Supports Page Attribute Table

PSE       * Supports 4 MB pages

PSE36     * Supports > 32-bit address 4 MB pages

PGE       * Supports global bit in page tables

SS         * Supports bus snooping for cache operations

VME       * Supports Virtual-8086 mode

FPU       * Implements i387 floating point instructions

MMX       * Supports MMX instruction set

MMXEXT     - Implements AMD MMX extensions

3DNOW     - Supports 3DNow! instructions

3DNOWEXT   - Supports 3DNow! extension instructions

SSE       * Supports Streaming SIMD Extensions

SSE2       * Supports Streaming SIMD Extensions 2

SSE3       * Supports Streaming SIMD Extensions 3

SSSE3     * Supports Supplemental SIMD Extensions 3

SSE4.1     * Supports Streaming SIMD Extensions 4.1

SSE4.2     - Supports Streaming SIMD Extensions 4.2

AES       - Supports AES extensions

AVX       - Supports AVX intruction extensions

FMA       - Supports FMA extensions using YMM state

MSR       * Implements RDMSR/WRMSR instructions

MTTR       * Supports Memory Type Range Registers

XSAVE     - Supports XSAVE/XRSTOR instructions

OSXSAVE   - Supports XSETBV/XGETBV instructions

CMOV       * Supports CMOVcc instruction

CLFSH     * Supports CLFLUSH instruction

CX8       * Supports compare and exchange 8-byte instructions

CX16       * Supprots CMPXCHG16B instruction

DCA       - Supports prefetch from memory-mapped device

F16C       - Supports half-precision instruction

FXSR       * Supports FXSAVE/FXSTOR instructions

FFXSR     - Supports optimized FXSAVE/FSRSTOR instruction

MONITOR   * Supports MONITOR and MWAIT instructions

MOVBE     - Supports MOVBE instruction

PCLULDQ   - Supports PCLMULDQ instruction

POPCNT     - Supports POPCNT instruction

SEP       * Supports fast system call instructions

DE         * Supports I/O breakpoints including CR4.DE

DTES64     * Can write history of 64-bit branch addresses

DS         * Implements memory-resident debug buffer

DS-CPL     * Supports Debug Store feature with CPL

PCID       - Supports PCIDs and settable CR4.PCIDE

PDCM       * Supports Performance Capabilities MSR

RDTSCP     - Supports RDTSCP instruction

TSC       * Supports RDTSC instruction

TSC-DEADLINE - Local APIC supports one-shot deadline timer

TSC-INVARIANT - TSC runs at constant rate

xTPR       * Supports disabling task priority messages

ACPI       * Implements MSR for power management

TM         * Implements thermal monitor circuitry

TM2       * Implements Thermal Monitor 2 control

APIC       * Implements software-accessible local APIC

x2APIC     - Supports x2APIC

CNXT-ID   - L1 data cache mode adaptive or BIOS

MCE       * Supports Machine Check, INT18 and CR4.MCE

MCA       * Implements Machine Check Architecture

PBE       * Supports use of FERR#/PBE# pin

PSN       - Implements 96-bit processor serial number

Logical to Physical Processor Map:

*-  Physical Processor 0

-*  Physical Processor 1

Logical Processor to Socket Map:

**  Socket 0

Logical Processor to NUMA Node Map:

**  NUMA Node 0

Logical Processor to Cache Map:

*-  Data Cache          0, Level 1,   32 KB, Assoc   8, LineSize  64

*-  Instruction Cache   0, Level 1,   32 KB, Assoc   8, LineSize  64

-*  Data Cache          1, Level 1,   32 KB, Assoc   8, LineSize  64

-*  Instruction Cache   1, Level 1,   32 KB, Assoc   8, LineSize  64

**  Unified Cache       0, Level 2,    6 MB, Assoc  24, LineSize  64

Hi Rajath,

Thanks to take care of my case. ^^

Optiplex 755

Coreinfo:

Intel(R) Core(TM)2 Duo CPU     E8500  @ 3.16GHz

x86 Family 6 Model 23 Stepping 6, GenuineIntel

HTT       * Hyperthreading enabled

HYPERVISOR - Hypervisor is present

VMX       * Supports Intel hardware-assisted virtualization

SVM       - Supports AMD hardware-assisted virtualization

EM64T     * Supports 64-bit mode

SMX       * Supports Intel trusted execution

SKINIT     - Supports AMD SKINIT

EIST       * Supports Enhanced Intel Speedstep

NX         * Supports no-execute page protection

PAGE1GB   - Supports 1 GB large pages

PAE       * Supports > 32-bit physical addresses

PAT       * Supports Page Attribute Table

PSE       * Supports 4 MB pages

PSE36     * Supports > 32-bit address 4 MB pages

PGE       * Supports global bit in page tables

SS         * Supports bus snooping for cache operations

VME       * Supports Virtual-8086 mode

FPU       * Implements i387 floating point instructions

MMX       * Supports MMX instruction set

MMXEXT     - Implements AMD MMX extensions

3DNOW     - Supports 3DNow! instructions

3DNOWEXT   - Supports 3DNow! extension instructions

SSE       * Supports Streaming SIMD Extensions

SSE2       * Supports Streaming SIMD Extensions 2

SSE3       * Supports Streaming SIMD Extensions 3

SSSE3     * Supports Supplemental SIMD Extensions 3

SSE4.1     * Supports Streaming SIMD Extensions 4.1

SSE4.2     - Supports Streaming SIMD Extensions 4.2

AES       - Supports AES extensions

AVX       - Supports AVX intruction extensions

FMA       - Supports FMA extensions using YMM state

MSR       * Implements RDMSR/WRMSR instructions

MTTR       * Supports Memory Type Range Registers

XSAVE     - Supports XSAVE/XRSTOR instructions

OSXSAVE   - Supports XSETBV/XGETBV instructions

CMOV       * Supports CMOVcc instruction

CLFSH     * Supports CLFLUSH instruction

CX8       * Supports compare and exchange 8-byte instructions

CX16       * Supprots CMPXCHG16B instruction

DCA       - Supports prefetch from memory-mapped device

F16C       - Supports half-precision instruction

FXSR       * Supports FXSAVE/FXSTOR instructions

FFXSR     - Supports optimized FXSAVE/FSRSTOR instruction

MONITOR   * Supports MONITOR and MWAIT instructions

MOVBE     - Supports MOVBE instruction

PCLULDQ   - Supports PCLMULDQ instruction

POPCNT     - Supports POPCNT instruction

SEP       * Supports fast system call instructions

DE         * Supports I/O breakpoints including CR4.DE

DTES64     * Can write history of 64-bit branch addresses

DS         * Implements memory-resident debug buffer

DS-CPL     * Supports Debug Store feature with CPL

PCID       - Supports PCIDs and settable CR4.PCIDE

PDCM       * Supports Performance Capabilities MSR

RDTSCP     - Supports RDTSCP instruction

TSC       * Supports RDTSC instruction

TSC-DEADLINE - Local APIC supports one-shot deadline timer

TSC-INVARIANT - TSC runs at constant rate

xTPR       * Supports disabling task priority messages

ACPI       * Implements MSR for power management

TM         * Implements thermal monitor circuitry

TM2       * Implements Thermal Monitor 2 control

APIC       * Implements software-accessible local APIC

x2APIC     - Supports x2APIC

CNXT-ID   - L1 data cache mode adaptive or BIOS

MCE       * Supports Machine Check, INT18 and CR4.MCE

MCA       * Implements Machine Check Architecture

PBE       * Supports use of FERR#/PBE# pin

PSN       - Implements 96-bit processor serial number

Logical to Physical Processor Map:

*-  Physical Processor 0

-*  Physical Processor 1

Logical Processor to Socket Map:

**  Socket 0

Logical Processor to NUMA Node Map:

**  NUMA Node 0

Logical Processor to Cache Map:

*-  Data Cache          0, Level 1,   32 KB, Assoc   8, LineSize  64

*-  Instruction Cache   0, Level 1,   32 KB, Assoc   8, LineSize  64

-*  Data Cache          1, Level 1,   32 KB, Assoc   8, LineSize  64

-*  Instruction Cache   1, Level 1,   32 KB, Assoc   8, LineSize  64

**  Unified Cache       0, Level 2,    6 MB, Assoc  24, LineSize  64

Hi Hollow_Beam,

Thank you for providing the requested information and apologize for the delay in responding to your request. We have sent the Coreinfo result to our Engineering Team and will provide appropriate information when we receive a reply from them.

Hi Hollow_Beam,

We have received a reply from our Engineering Team saying that as per the report provided by you, the option has been enabled. Please install and check the RTM version of Windows 8 on your computer. If you experience the same issue, please reply to this message. We will escalate it again to get a fix for it.

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