Chip Densities | 512 Mb-8 Gb | 4 Gb-16 Gb | Larger DIMM capacities |
Data rates | 800 Mb/s-2133 Mb/s | 1600 Mb/s-3200 Mb/s | Migration to higher speed I/O |
Voltage | 1.5 V | 1.2 V | Reduced memory power demand |
Low voltage standard | Yes (DDR3L at 1.35V) | Anticipated at 1.05V | Memory Power Reductions |
Internal banks | 8 | 16 | Higher data rates |
Bank groups (BG) | 0 | 4 | Faster burst accesses |
VREF inputs | 2 —DQs and CMD/ADDR | 1 — CMD/ADDR | VREFDQ Now Internal |
tCK — DLL Enabled | 300 Mhz-800 Mhz | 667Mhz-1.6Ghz | Higher data rates |
tCK — DLL Disabled | 10MHz – 125MHz (optional) | Undefined to 125MHz | DLL-off now fully supported |
Read Latency | AL+CL | AL+CL | Expanded values |
Write Latency | AL+CWL | AL+CWL | Expanded values |
DQ Driver (ALT) | 40&Omega | 48&Omega | Optimal for PtP Applications |
DQ Bus | SSTL15 | POD12 | Less I/O Noise and Power |
RTT Values (in Ω) | 120,60,40,30,20 | 240,120,80,60,48,40,34 | Support for higher data rates |
RTT not allowed | READ Bursts | Disables during READ Bursts | Ease of use |
ODT Modes | Nominal, Dynamic | Nominal, Dynamic,Park | Add’l Control Mode; OTF Value Change |
ODT Control | ODT Signaling Required | ODT Signaling Not Required | Ease of ODT Control; Allows Non-ODT Routing, PtP
Apps
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Multi-Purpose Register | Four Registers – 1 Defined, 3 RFU | Four Registers – 3 Defined, 1 RFU | Provides Additional Specialty Readout |
DIMM Types | RDIMM, LRDIMM, UDIMM, SODIMM | RDIMM, LRDIMM, UDIMM, SODIMM | |
DIMM Pins | 240 (R, LR, U); 204 (SODIMM) | 288 (R, LR, U); 260 (SODIMM) | |
RAS | ECC | CRC, Parity, Addressability, GDM | More RAS features; improved data integrity |