Dell EMC PowerEdge R6515 BIOS and UEFI Reference Guide

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Processor Settings

To view the Processor Settings screen, power on the system, press F2, and click System Setup Main Menu > System BIOS > Processor Settings.

Table 1. Processor Settings detailsThis table provides the details of the options available on the Processor Settings screen.
Option	Description
Logical Processor	Each processor core supports up to two logical processors. If this option is set to Enabled, the BIOS displays all the logical processors. If this option is set to Disabled, the BIOS displays only one logical processor per core. This option is set to Enabled by default.
Virtualization Technology	Enables or disables the virtualization technology for the processor. This option is set to Enabled by default.
IOMMU Support	Enable or Disable IOMMU support. It is required to create IVRS ACPI table. This option is set to Enabled by default.
Kernel DMA Protection	When this option is set to Enabled, using IOMMU, BIOS, and the Operating System will enable direct memory access protection for DMA capable peripheral devices. Enable IOMMU Support to use this option. When this option is set to Enabled, using Virtualization Technology, BIOS, and the Operating System will enable direct memory access protection for DMA capable peripheral devices. Enable Virtualization Technology to use this option. This option is set to Disabled by default.
L1 Stream HW Prefetcher	Enables or disables the L1 stream hardware prefetcher. This option is set to Enabled by default.
L2 Stream HW Prefetcher	Enables or disables the L2 stream hardware prefetcher. This option is set to Enabled by default.
L1 Stride Prefetcher	Enables or disables the L1 stride prefetcher. This option is set to Enabled by default, as it optimizes overall workload. NOTE This option is only available for 3rd Generation AMD EPYC processors.
L1 Region Prefetcher	Enables or disables the L1 region prefetcher. This option is set to Enabled by default, as it optimizes overall workload. NOTE This option is only available for 3rd Generation AMD EPYC processors.
L2 Up Down Prefetcher	Enables or disables the L2 up down prefetcher. This option is set to Enabled by default, as it optimizes overall workload. NOTE This option is only available for 3rd Generation AMD EPYC processors.
MADT Core Enumeration	Specifies the MADT Core Enumeration. This option is set to Linear by default.
NUMA Nodes Per Socket	Specifies the number of NUMA nodes per socket. This option is set to 1 by default.
L3 cache as NUMA Domain	Enables or disables the CCX as NUMA Domain. This option is set to Disabled by default.
Secure Memory Encryption (SME)	Enables or disables the AMD secure encryption features such as SME and Secure Encrypted Virtualization (SEV). It also determines if other secure encryption features such as TSME and SEV-SNP can be enabled. This option is set to Disabled by default. NOTE This option is only available for 3rd Generation AMD EPYC processors.
Minimum SEV non-ES ASID	Determines the number of Secure Encrypted Virtualization ES and non-ES available Address Space IDs. This option is set to 1 by default.
Secured Nested Paging (SNP)	Enables or disables SEV-SNP, a set of additional security protections. This option is set to Disabled by default. NOTE This option is only available for 3rd Generation AMD EPYC processors.
SNP Memory Coverage	This option selects the operating mode of the Nested Paging (SNP) Memory and the reverse Map Table(RMP). The RMP is used to ensure a one-to-one mapping between system physical addresses and guest physical addresses. NOTE This option is only available for 3rd Generation AMD EPYC processors.
Transparent Secure Memory Encryption (TSME)	Enables or disables the TSME. TSME is always-on memory encryption that does not require OS or hypervisor support. This option is set to Disabled by default. If the OS supports SME, do not enable this field. If the hypervisor supports SEV, do not enable this field. Enabling TSME affects the system memory performance.
Enhanced REP MOVSB/STOSB	Enables or disables Enhanced REP MOVSB/STOSB support. This setting can affect performance, depending on the application running on the server. This option is set to Disabled by default. NOTE This option is only available for the AMD EPYC 7003 processor.
Fast Short REP MOVSB	Enables or disables Fast Short REP MOVSB support. This setting can affect performance, depending on the application running on the server. This option is set to Disabled by default. NOTE This option is only available for the AMD EPYC 7003 processor.
REP-MOV/STOS Streaming	Enables or disables REP MOVISTOS Streaming support. This setting can affect performance, depending on the application running on the server. This option is set to Disabled by default. NOTE This option is only available for the AMD EPYC 7003 processor.
Configurable TDP	Allows the reconfiguration of the processor Thermal Design Power (TDP) levels based on the power and thermal delivery capabilities of the system. TDP refers to the maximum amount of power the cooling system is required to dissipate. This option is set to Maximum by default. NOTE This option is only available on certain SKUs of the processors, and the number of alternative levels varies as well.
x2APIC Mode	Enables or disables x2APIC mode. This option is set to Enabled by default. NOTE For two CPU 64 cores configuration, x2APIC mode is not switchable if 256 threads are enabled (BIOS settings: All CCD, cores, and logical processors enabled).
Number of CCDs per Processor	Controls the number of enabled CCDs in each processor. This option is set to All by default.
Number of Cores per CCD	Specifies the number of cores per CCD. This option is set to All by default.
Processor Core Speed	Specifies the maximum core frequency of the processor.
Processor n	NOTE Depending on the number of CPUs, there might be up to n processors listed. The following settings are displayed for each processor that is installed in the system:

Table 2. Processor n detailsThis table describes the settings available for each processor.
Option	Description
Family-Model-Stepping	Specifies the family, model, and stepping of the processor as defined by AMD.
Brand	Specifies the brand name.
Level 2 Cache	Specifies the total L2 cache.
Level 3 Cache	Specifies the total L3 cache.
Number of Cores	Specifies the number of cores per processor.
Microcode	Specifies the processor microcode version.