System Event I/O channel chk.
|
Critical |
This event is generated when a critical interrupt is generated
in the I/O Channel.
|
System Event PCI Parity Err.
|
Critical |
This event is generated when a parity error is detected on
the PCI bus.
|
System Event Chipset Err.
|
Critical |
This event is generated when a chip error is detected. |
System Event PCI System Err.
|
Information |
This event indicates historical data, and is generated when
the system has crashed and recovered.
|
System Event PCI Fatal Err.
|
Critical |
This error is generated when a fatal error is detected on the
PCI bus.
|
System Event PCIE Fatal Err.
|
Critical |
This error is generated when a fatal error is detected on the
PCIE bus.
|
POST Err.
|
Critical |
This event is generated when an error occurs during system
boot. See the system documentation for more information on the error
code.
|
POST fatal error #<number> or <error description>.
|
Critical |
This event is generated when a fatal error occurs during system
boot. For more information, see
POST Code Errors.
|
Memory Spared redundancy lost.
|
Critical |
This event is generated when memory spare is no longer redundant. |
Memory Mirrored redundancy lost.
|
Critical |
This event is generated when memory mirroring is no longer
redundant.
|
Memory RAID redundancy lost.
|
Critical |
This event is generated when memory RAID is no longer redundant. |
Err Reg Pointer OEM Diagnostic data event was asserted.
|
Information |
This event is generated when an OEM event occurs. OEM events
can be used by the service team to better understand the cause of
the failure.
|
System Board PFault Fail Safe state asserted.
|
Critical |
This event is generated when the system board voltages are
not at normal levels.
|
System Board PFault Fail Safe state deasserted
|
Information |
This event is generated when earlier PFault Fail Safe system
voltages return to a normal level.
|
Memory Add (BANK# DIMM#) presence was asserted.
|
Information |
This event is generated when memory is added to the system. |
Memory Removed (BANK# DIMM#) presence was asserted.
|
Information |
This event is generated when memory is removed from the system. |
Memory Cfg Err configuration error (BANK# DIMM#) was
asserted.
|
Critical |
This event is generated when memory configuration is incorrect
for the system.
|
Mem Redun Gain redundancy regained.
|
Information |
This event is generated when memory redundancy is regained. |
Mem ECC Warning transition to non-critical from OK.
|
Warning |
This event is generated when correctable ECC errors have increased
from a normal rate.
|
Mem ECC Warning transition to critical from less severe.
|
Critical |
This event is generated when correctable ECC errors reach a
critical rate.
|
Mem CRC Err transition to non-recoverable.
|
Critical |
This event is generated when CRC errors enter a non-recoverable
state.
|
Mem Fatal SB CRC uncorrectable ECC was asserted.
|
Critical |
This event is generated while storing CRC errors to memory. |
Mem Fatal NB CRC uncorrectable ECC was asserted.
|
Critical |
This event is generated while removing CRC errors from memory. |
Mem Overtemp critical over temperature was asserted.
|
Critical |
This event is generated when system memory reaches critical
temperature.
|
USB Over-current transition to non-recoverable
|
Critical |
This event is generated when the USB exceeds a predefined current
level.
|
Hdwr version err hardware incompatibility (BMC/iDRAC
Firmware and CPU mismatch) was asserted.
|
Critical |
This event is generated when there is a mismatch between the
BMC and iDRAC firmware and the processor in use or vice versa.
|
Hdwr version err hardware incompatibility (BMC/iDRAC
Firmware and CPU mismatch) was deasserted.
|
Information |
This event is generated when an earlier mismatch between the
BMC and iDRAC firmware and the processor is corrected.
|
SBE Log Disabled correctable memory error logging disabled
was asserted.
|
Critical |
This event is generated when the ECC single bit error rate
is exceeded.
|
CPU Protocol Err transition to non-recoverable.
|
Critical |
This event is generated when the processor protocol enters
a non-recoverable state.
|
CPU Bus PERR transition to non-recoverable.
|
Critical |
This event is generated when the processor bus PERR enters
a non-recoverable state.
|
CPU Init Err transition to non-recoverable.
|
Critical |
This event is generated when the processor initialization enters
a non-recoverable state.
|
CPU Machine Chk transition to non-recoverable.
|
Critical |
This event is generated when the processor machine check enters
a non-recoverable state.
|
Logging Disabled all event logging disabled was asserted.
|
Critical |
This event is generated when all event logging is disabled. |
LinkT/FlexAddr: Link Tuning sensor, device option ROM
failed to support link tuning or flex address (Mezz XX) was asserted
|
Critical |
This event is generated when the PCI device option ROM for
a NIC does not support link tuning or the Flex addressing feature.
|
LinkT/FlexAddr: Link Tuning sensor, failed to program
virtual MAC address (<location>) was asserted.
|
Critical |
This event is generated when BIOS fails to program virtual
MAC address on the given NIC device.
|
PCIE NonFatal Er: Non Fatal IO Group sensor, PCIe error(<location>)
|
Warning |
This event is generated in association with a CPU IERR. |
I/O Fatal Err: Fatal IO Group sensor, fatal IO error
(<location>)
|
Critical |
This event is generated in association with a CPU IERR and
indicates the PCI/PCIe device that caused the CPU IERR.
|
Unknown system event sensor unknown system hardware
failure was asserted.
|
Critical |
This event is generated when an unknown hardware failure is
detected.
|
An I/O channel check error was detected.
|
Critical |
This event is generated when a critical interrupt is generated
in the I/O Channel.
|
A PCI parity error was detected on a component at bus
<number> device <number> function <number>.
|
Critical |
This event is generated when a parity error is detected on
the PCI bus.
|
A PCI parity error was detected on a component at slot
<number>.
|
Critical |
This event is generated when a parity error is detected on
the PCI bus.
|
A PCI system error was detected on a component at bus
<number> device <number> function <number>.
|
Critical |
This is generated when the system has crashed and recovered. |
A PCI system error was detected on a component at slot
<number>.
|
Critical |
This is generated when the system has crashed and recovered. |
A bus correctable error was detected on a component
at bus <number> device <number> function <number>.
|
Critical |
This is generated when the system has detected bus correctable
errors.
|
A bus correctable error was detected on a component
at slot <number>.
|
Critical |
This is generated when the system has detected bus correctable
errors.
|
A bus uncorrectable error was detected on a component
at bus <number> device <number> function <>number>.
|
Critical |
This is generated when the system has detected bus uncorrectable
errors.
|
A bus uncorrectable error was detected on a component
at slot <number>.
|
Critical |
This is generated when the system has detected bus uncorrectable
errors.
|
A fatal error was detected on a component at bus <number>
device <number> function <number>.
|
Critical |
This error is generated when a fatal error is detected on the
PCI bus.
|
A fatal error was detected on a component at slot <number>.
|
Critical |
This error is generated when a fatal error is detected on the
PCI bus.
|
A fatal IO error detected on a component at bus <number>
device <number> function <number>.
|
Critical |
This error is generated when a fatal IO error is detected. |
A fatal IO error detected on a component at slot <number>.
|
Critical |
This error is generated when a fatal IO error is detected. |
A non-fatal PCIe error detected on a component at bus
<number> device <number> function <number>.
|
Warning |
This event is generated in association with a CPU IERR. |
A non-fatal PCIe error detected on a component at slot
<number>.
|
Warning |
This event is generated in association with a CPU IERR. |
A non-fatal IO error detected on a component at bus
<number> device <number> function <number>.
|
Warning |
This event is generated in association with a CPU IERR and
indicates the PCI/PCIe device that caused the CPU IERR.
|
Memory device was added at location <location>.
|
Information |
This event is generated when memory is added to the system. |
Memory device is removed from location <location>.
|
Information |
This event is generated when memory is removed from the system. |
Unsupported memory configuration; check memory device
at location <location>.
|
Critical |
This event is generated when memory configuration is incorrect
for the system.
|
Correctable memory error rate exceeded for <location>.
|
Warning |
This event is generated when correctable ECC errors have increased
from a normal rate.
|
Correctable memory error rate exceeded for <location>.
|
Critical |
This event is generated when correctable ECC errors reach a
critical rate.
|
Memory device at location <location> is overheating.
|
Critical |
This event is generated when system memory reaches critical
temperature.
|
An OEM diagnostic event occurred.
|
Information |
This event is generated when an OEM event occurs. OEM events
can be used by the service team to better understand the cause of
the failure.
|
CPU <number> protocol error detected.
|
Critical |
This event is generated when the processor protocol enters
a non-recoverable state.
|
CPU bus parity error detected.
|
Critical |
This event is generated when the processor bus PERR enters
a non-recoverable state.
|
CPU <number> initialization error detected.
|
Critical |
This event is generated when the processor initialization enters
a non-recoverable state.
|
CPU <number> machine check error detected.
|
Critical |
This event is generated when the processor machine check enters
a non-recoverable state.
|
All event logging is disabled.
|
Critical |
This event is generated when all event logging is disabled. |
Logging is disabled.
|
Critical |
This event is generated when the ECC single bit error rate
is exceeded.
|
The system board fail-safe voltage is outside of range.
|
Critical |
This event is generated when the system board voltages are
not at normal levels.
|
The system board fail-safe voltage is within range.
|
Information |
This event is generated when earlier Fail-Safe system voltages
return to a normal level.
|
A hardware incompatibility detected between BMC/iDRAC
firmware and CPU.
|
Critical |
This event is generated when there is a mismatch between the
BMC and iDRAC firmware and the processor in use or vice versa.
|
A hardware incompatibility was corrected between BMC/
iDRAC firmware and CPU.
|
Information |
This event is generated when an earlier mismatch between the
BMC and iDRAC firmware and the processor is corrected.
|
Device option ROM on embedded NIC failed to support
Link Tuning or FlexAddress.
|
Critical |
This event is generated when the PCI device option ROM for
a NIC does not support link tuning or the Flex addressing feature.
|
Device option ROM on mezzanine card <number> failed
to support Link Tuning or FlexAddress.
|
Critical |
This event is generated when the PCI device option ROM for
a NIC does not support link tuning or the Flex addressing feature.
|
Failed to program virtual MAC address on a component
at bus <bus> device <device> function <function>.
|
Critical |
This event is generated when BIOS fails to program virtual
MAC address on the given NIC device.
|
Failed to get Link Tuning or FlexAddress data from
iDRAC.
|
Critical |
This event is generated when BIOS could not obtain virtual
MAC address or Link Tuning data from iDRAC.
|
An unknown system hardware failure detected.
|
Critical |
This event is generated when an unknown hardware failure is
detected.
|
POST fatal error <error description>
|
Critical |
This event is generated when a fatal error occurs during system
boot. For more information, see
POST Code Errors.
|